晶片設計工程師-靜電放電

晶片設計工程師-靜電放電

工作內容 :



Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis.


薪金 :

每月$18,000 - $25,000, 有雙糧, 酌情性花紅, 醫療福利, 表現獎金 及Family caring measures...

要求學歷 :

專上教育：學士學位; 良好粵語; 良好普通話; 良好英語; 懂讀寫中文; 懂讀寫英文; Electronic Engineering,Knowledge about semiconductor and Verilog-based logic design and synthesis